View CXP84632_113778.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP84632/84640/84648
CMOS 8-bit Single Chip Microcomputer
Description The CXP84632/84640/84648 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, I2C bus interface, remote control reception circuit, PWM output, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP84632/84640/84648 also provides a sleep/ stop function that enables lower power consumption. 80 pin QFP (Plastic)
Features * Wide range instruction system (213 instructions) to cover various of data. -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (3.0 to 5.5V) 122s at 32kHz operation (2.7 to 5.5V) * Incorporated ROM capacity 32K bytes (CXP84632) 40K bytes (CXP84640) 48K bytes (CXP84648) * Incorporated RAM capacity 2048 bytes * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time 20s/16MHz) -- Serial interface Srart-stop synchronization (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit, 10-stage FIFO (Auto transfer for 1 to 10 bytes), 1 channel 8-bit clock syncronization (MSB/LSB first selectable), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32kHz timer/counter 2C bus interface --I -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO -- PWM output circuit 12 bits, 2 channels * Interruption 21 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 80-pin plastic QFP * Piggyback/evaluation chip CXP84600 80-pin ceramic QFP
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96309-ST
Block Diagram
AVREF
TEX
AVSS
NMI INT0 INT1 INT2 INT3 INT4
EXTAL XTAL RST VDD VSS
AN0 to AN7 8 SPC 700 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROL
8
A/D CONVERTER
NMI
TX
PA0 to PA7
RxD
UART RECEIVER
TxD
UART TRANSMITTER
8
PB0 to PB7
UART BAUD RATE GENERATOR
PWM0 PWM1 FIFO ROM 32K/40K/48K BYTES RAM 2048 BYTES
12 BIT PWM GENERATOR 0
8
PC0 to PC7
12 BIT PWM GENERATOR 1
INTERRUPT CONTROLLER
RMC
REMOCON IN
8 4 2 7
PD0 to PD7 PE0 to PE3 PE4 to PE5 PF0 to PF6 PF7
CS0 SI0 SO0 SCK0 BUFFER RAM FIFO
SERIAL INTERFACE UNIT (CH0)
SCL0 SCL1 SDA0 SDA1
I2C BUS INTERFACE UNIT
CXP84632/84640/84648
ADJ
2
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
-2-
PRESCALER/ TIME BASE TIMER 2 2
SI1 SO1 SCK1
SERIAL INTERFACE UNIT (CH1)
SI2 SO2 SCK2
SERIAL INTERFACE UNIT (CH2)
32kHz TIMER/COUNTER
8
PG0 to PG7
EC0
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
8
PH0 to PH7
TO CINT EC1
16 BIT CAPTURE TIMER/COUNTER 2
8
PI0 to PI7
CXP84632/84640/84648
Pin Assignment (Top View)
PF2/SDA0
PF1/SCL1
PF0/SCL0
PI7/SO2
PG7
PG6
PG5
PG4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3/SDA0 PF4/PWM0 PF5/PWM1 PF6/TxD PF7/RxD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4/INT4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/ADJ PE4 PE3/NMI PE2/RMC PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CINT PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3
NC
VDD
PG3
PG2
PG1
PG0
PI6/SI2 PA1/AN1
Note) NC (Pin 73) must be connected VDD.
-3-
PA0/AN0
PA2/AN2
EXTAL
AVREF
XTAL
AVSS
RST
PH3
PH4
PH5
PH6
PH7
TEX
VSS
TX
PI5/SCK2
CXP84632/84640/84648
Pin Description Pin code I/O (Port A) 8-bit I/O port. I/O can be set in a unit of signle bits. Incorporation of the pullup resistance can be set through the software in a unit of 4 bits. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/Analog input
Analog inputs to A/D converter. (8 pins)
PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port B) I/O can be set in a unit of single bits for lower 7 bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input.
PC0 to PC7
I/O
PD0 to PD7
I/O
PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PE4 PE5/TO/ ADJ PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1 PF4/PWM0 PF5/PWM1 PF6/TxD PF7/RxD
Input/Input Input/Input Input/Input Input/Input Output Output/Output/ Output Output/I/O Output/I/O Output/Output Output/Output Output/Output Input/Input (Port F) Lower 7 bits are for output; of which lower 4 bits are large current (12mA) N-ch open drain output. The uppermost bit (PF7) is for input. (8pins)
Rectangular wave output for 16-bit timer/counter. Output for 32kHz oscillation frequency division. Transfer clock I/O for I2C bus interface. (2pins) Transfer data I/O for I2C bus interface. (2pins) PWM outputs. (2pins) UART transmission data output. UART reception data input.
-4-
CXP84632/84640/84648
Pin code
I/O
Functions (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (5 pins) Serial clock I/O. (CH2) Serial data input. (CH2) Serial data output. (CH2)
PG0 to PG7
I/O
PH0 to PH7
I/O
PI0/INT0 to PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 EXTAL XTAL TEX TX RST NC AVREF AVss VDD Vss
I/O/Input I/O/I/O I/O/Input I/O/Output Input Output Input Output Input
Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event counter, input to TEX, and open TX. Low-level active, system reset. NC. Under normal operating conditions, connect to VDD.
Input
Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND.
-5-
CXP84632/84640/84648
I/O Circuit Format for Pins Pin Port A
Pull-up resistance "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Port A direction "0" when reset Data bus RD (Port A) Port A function selection "0" when reset A/D converter
IP
Input protection circuit
Hi-Z
Input multiplexer Pull-up transistors approx. 100k
8 pins Port B Port I
Pull-up resistance "0" when reset
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 PI6/SI2
Port B, I data
Port B, I direction "0" when reset Data bus RD (Port B, I) CINT CS0 SI0 SI1 Schmitt input
IP
Hi-Z
5 pins Port B Port I
Pull-up resistance "0" when reset SCK OUT Serial clock output enable Port B, I function selection
Pull-up transistors approx. 100k
PB2/SCK0 PB5/SCK1 PI5/SCK2
"0" when reset Port B, I data Port B, I direction "0" when reset Data bus RD (Port B, I) Schmitt input IP
Hi-Z
3 pins
SCK in
Pull-up transistors approx. 100k
-6-
CXP84632/84640/84648
Pin Port B Port I
Pull-up resistance "0" when reset SO Serial data output enable Port B, I function selection
Circuit format
When reset
PB4/SO0 PB7/SO1 PI7/SO2
"0" when reset Port B, I data Port B, I direction "0" when reset Data bus RD (Port B, I) Pull-up transistors approx. 100k IP
Hi-Z
3 pins Port C
Pull-up resistance "0" when reset Port C data
2
PC0 to PC7
Port C direction "0" when reset Data bus RD (Port C) 1 Large current 12mA 2 Pull-up transistors approx. 100k 1
Hi-Z
IP
8 pins Port E Port F
IP Schmitt input
PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PF7/RxD 5 pins
EC0, EC1, RMC, NMI, RxD Data bus RD (Port E, F)
Hi-Z
Port E
PE4
Port E data "1" when reset Data bus
High level
1 pin
RD (Port E)
-7-
CXP84632/84640/84648
Pin Port E
Circuit format
Internal reset signal Port E data "1" when reset TO ADJ16K1 ADJ2K1 00 01 10 11 MPX 2
When reset
PE5/TO/ADJ
Port E function selection (upper) Port E function selection (lower) "00" when reset TO output enable 1 ADJ signals are frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. 2 Pull-up transistor approx. 150k
(
High level with approx. 150k resistor when reset
)
1 pin Port D Port G Port H PD0 to PD7 PG0 to PG7 PH0 to PH7
Pull-up resistance "0" when reset Port D, G, H data
Port D, G, H direction "0" when reset Data bus
IP
Hi-Z
24 pins Port I
RD (Port D, G, H)
Pull-up transistors approx. 100k
Pull-up resistance "0" when reset Port I data
PI0/INT0 to PI4/INT4
Data bus
Port I direction "0" when reset
IP
Hi-Z
RD (Port I)
5 pins
INT0 INT1 INT2 INT3 INT4
Pull-up transistors approx. 100k
-8-
CXP84632/84640/84648
Pin Port F
SCL, SDA I2C output enable ("0" when reset) Port F data "1" when reset
Circuit format
When reset
PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1
IP Schmitt input
Hi-Z
BUS SW To internal I2C pin (SCL1 for SCL0)
SCL, SDA (To I2C circuit)
4 pins Port F
PWM Port F output selection
Large current 12mA
PF4/PWM0 PF5/PWM1
"0" when reset Port F data "1" when reset Data bus
High level
2 pins Port F
RD (Port F)
UART transmission circuit Port F output selection
PF6/TxD
"0" when reset
High level
Port F data "1" when reset Data bus RD (Port F)
1 pin Port H
Port H data "0" when reset Port H direction
PH0 to PH7
Data bus RD (Port H) Standby release Data bus Edge detection
IP
Hi-Z
8 pins
RD (Port H direction)
-9-
CXP84632/84640/84648
Pin
Circuit format
When reset
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop, and XTAL becomes High level.
Oscillation
2 pins
XTAL
TEX TX
* Diagram shows circuit composition during oscillation. TEX IP IP * When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become Low level and High level respectively.
Oscillation
2 pins
TX
Pull-up resistor
RST
OP
Mask option IP Schmitt input
Low level
1 pin
- 10 -
CXP84632/84640/84648
Absolute Maximum Ratings Item Supply voltage Input voltagte Output voltage High level output current Symbol VDD AVSS VIN VOUT IOH Rating -0.3 to +7.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V mA mA mA mA mA C C mW
(Vss = 0V reference) Remarks
Output (value per pin) Total for all output pins All pins excluding large current outputs (value per pin) Large current outputs (value per pin) 2 Total for all output pins
High level total output current IOH Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL IOLC IOL Topr Tstg PD
1 VIN and VOUT must not exceed VDD + 0.3V. 2 The large current output is for each pin of Port C (PC), Port F0 (PF0) to Port 3 (PF3). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
- 11 -
CXP84632/84640/84648
Recommended Operating Conditions Item Symbol Min. 4.5 3.0 Supply voltage VDD 2.7 2.7 2.5 VIH HIgh level input voltage VIHS VIHEX 0.7VDD 0.8VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V V V C
(Vss = 0V reference) Remarks fc = 16MHz or less Guaranteed operation range for 1/2 and 1/4 fc = 12MHz or less frequency dividing clock. Guaranteed operation range for 1/16 frequency dividing clock or SLEEP mode Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP 1, 5 1, 6 Hysteresis input2 EXTAL pin3, 5 TEX pin4, 5 EXTAL pin3, 6 TEX pin4, 6 1, 5 1, 6 Hysteresis input2 EXTAL pin3, 5 TEX pin4, 5 EXTAL pin3, 6 TEX pin4, 6
VDD - 0.4 VDD + 0.3 VDD - 0.2 VDD + 0.2
VIL Low level input voltage VILS VILEX Operating temperature Topr
0 0 0 -0.3 -0.3 -20
0.3VDD 0.2VDD 0.2VDD 0.4 0.2 +75
1 Normal input port (each pin of PA, PB4, PB7, PC, PF0 to PF4, PG, PH and PI7) 2 Each pin of RST, CINT, CS0, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, RMC, NMI, RxD, INT0, INT1, INT2, INT3 and INT4 3 It is specified only when the external clock is input. 4 It is specified only when the external event count clock is input. 5 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). 6 This case applies to the range of 3.0 to 5.5V supply voltage (VDD).
- 12 -
CXP84632/84640/84648
Electrical Characteristics DC Characteristics Supply voltage (VDD) 4.5 to 5.5V Item Symbol Pins PA to PD, PE4, PE5, PF4, PF5, PF6, PG to PI Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 -0.5 0.1 -0.1 -1.5 40 -40 10 -10 -400 -45 VDD = 4.5V, VIL = 4.0V VDD = 5.5V VI = 0, 5.5V -2.78 10 Typ. Max. Unit V V V V V V V A A A A A A A A
High level VOH output voltage
Low level output voltage VOL
PC, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA PF0 to PF3 VDD = 4.5V, IOL = 3.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA
IIHE IILE IIHT Input current IILT IILR IIL I/O lealage current TEX RST1 PA to PD2, PG to PI2 PA to PD2, PG to PI2, RST1 EXTAL
VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V
IIZ
Open drain output leakage ILOH current (N-ch Tr off state) I2C bus switch connection impedance RBS (Output Tr off state)
PF0 to PF3 VDD = 5.5V (SCL0, SCL1, VOH = 5.5V SDA0, SDA1)
10
A
SCL0: SCL1 SDA0: SDA1
VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V
120
- 13 -
CXP84632/84640/84648
Item
Symbol IDD1
Pins
Conditions 1/2 frequency dividing clock operation VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation; and termination of 16MHz oscillation (C1 = C2 = 47pF) SLEEP mode
Min.
Typ. 31
Max. 50
Unit mA
IDD2 Supply current3
40
100
A
IDDS1
VDD
VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation; and termination of 16MHz oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation
2.5
10
mA
IDDS2
8
30
A
IDDS3
10
A
Input capacity
CIN
PA to PC, PE0 to PE5, Clock 1MHz PF to PI, 0V for all pins excluding measured EXTAL, pins TEX, RST
10
20
pF
1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 2 PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 3 When all pins are open.
- 14 -
CXP84632/84640/84648
Electrical Characteristics DC Characteristics Supply voltage (VDD) 3.0 to 3.6V Item Symbol Pins PA to PD, PE4, PE5, PF4, PF5, PF6 Conditions VDD = 3.0V, IOH = -0.15mA VDD = 3.0V, IOH = -0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA (Ta = -20 to +75C, Vss = 0V reference) Min. 2.7 2.3 0.3 0.5 1 0.3 0.5 0.3 -0.3 0.1 -0.1 -0.9 20 -20 10 -10 -200 -20 VDD = 3.0V, VIL = 2.7V VDD = 3.6V VI = 0, 3.6V -1.0 10 Typ. Max. Unit V V V V V V V A A A A A A A A
High level VOH output voltage
Low level output voltage VOL
PC, PF0 to PF3 VDD = 3.0V, IOL = 5.0mA PF0 to PF3 VDD = 3.0V, IOL = 2.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 3.0V, IOL = 2.5mA
IIHE IILE IIHT Input current IILT IILR IIL I/O lealage current TEX RST1 PA to PD2, PG to PI2 PA to PD2, PG to PI2, RST1 EXTAL
VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 3.6V VDD = 3.6V, VIL = 0.4V VDD = 3.6V, VIL = 0.3V
IIZ
Open drain output leakage ILOH current (N-ch Tr off state) I2C bus switch connection impedance RBS (Output Tr off state)
PF0 to PF3 VDD = 3.6V (SCL0, SCL1, VOH = 3.6V SDA0, SDA1)
10
A
SCL0: SCL1 SDA0: SDA1
VDD = 3.0V VSCL0 = VSCL1 = 1.5V VSDA0 = VSDA1 = 1.5V
300
- 15 -
CXP84632/84640/84648
Item
Symbol IDD1
Pins
Conditions 1/2 frequency dividing clock operation VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) SLEEP mode
Min.
Typ. 11
Max. 25
Unit mA
Supply current3
IDDS1
VDD
VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) STOP mode VDD = 3.6V, termination of 16MHz and 32kHz crystal oscillation
0.5
2.5
mA
IDDS3
10
A
Input capacity
CIN
PA to PC, PE0 to PE5, Clock 1MHz 0V for all pins excluding measured PF to PI, pins EXTAL, TEX, RST
10
20
pF
1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 2 PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 3 When all pins are open.
- 16 -
CXP84632/84640/84648
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time, fall time 1 Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions
VDD = 4.5 to 5.5V
Min. 1 1
Typ.
Max. 16 12
Unit MHz
Fig. 1, Fig. 2 Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3
tXL tXH tCR tCF tEH tEL tER tEF
fC
28 37.5 200 4tsys1 20
ns ns ns ms
32.768
kHz
tTL tTH tTR tTF
10 20
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (Upper two bits = "11")
Fig. 1. Clock timing
1/fc
EXTAL
VDD - 0.4V (VDD = 4.5 to 5.5V) VDD - 0.3V 0.4V (VDD = 4.5 to 5.5V) 0.3V tXH tCF tXL tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL
TEX
TX
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC0 EC1
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
- 17 -
CXP84632/84640/84648
(2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (against SCK) SI input hold time (against SCK) SCK SO delay time Note 1) Symbol Pin SCK0 SCK0 SO0 SO0 CS0 SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
SCK0
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
SI0
SI0
SO0
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
- 18 -
CXP84632/84640/84648
Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (against SCK) SI input hold time (against SCK) SCK SO delay time Note 1) Symbol Pin SCK0 SCK0 SO0 SO0 CS0 SCK0
(Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns
tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO
tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200
2tsys + 200 16000/fc
SCK0
tsys + 100
8000/fc - 150 -tsys + 100 200 2tsys + 100 100
SI0
SI0
SO0
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11")
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF.
- 19 -
CXP84632/84640/84648
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
- 20 -
CXP84632/84640/84648
Serial transfer (CH1, CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (against SCK) SI input hold time (against SCK) SCK SO delay time Note 1) Symbol Pin SCK1 SCK2 SCK1 SCK2 SI1 SI2 SI1 SI2 SO1 SO2
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01'), 16000/fc (Upper 2 bits = "11") Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and SO2, respectively for CH2. Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF+1TTL.
Serial transfer (CH1, CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (against SCK) SI input hold time (against SCK) SCK SO delay time Note 1) Symbol Pin SCK1 SCK2 SCK1 SCK2 SI1 SI2 SI1 SI2 SO1 SO2
(Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V reference) Condition Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 150 100 200
tsys + 200
100
tsys + 250
125
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01'), 16000/fc (Upper 2 bits = "11")
Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and SO2, respectively for CH2. Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF.
- 21 -
CXP84632/84640/84648
Fig. 5. Serial transfer CH1 and CH2 timing
tKCY tKL tKH
0.8VDD SCK1 SCK2 0.2VDD
tSIK
tKSI
0.8VDD SI1 SI2 Input data 0.2VDD
tKSO
0.8VDD SO1 SO2 0.2VDD Output data
- 22 -
CXP84632/84640/84648
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = 3.0 to 5.5V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity errror Zero transition voltage Full-scale transition voltage Linearity errror Zero transition voltage Full-scale transition voltage Convertion time Sampling time Reference input voltage Analog input voltage VZT1 VFT2 Ta = 25C VDD = AVREF = 3.3V VSS = AVSS = 0V -10 3215 160/fADC3 12/fADC3 VDD = 4.5 to 5.5V AVREF AN0 to AN7 Operation VDD = 5.5V mode VDD = 3.6V AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VDD = 3.0 to 3.6V VDD - 0.5 VDD - 0.3 0 0.6 0.4 VDD VDD AVREF 1.0 0.7 10 6.5 3280 VZT1 VFT2 Ta = 25C VDD = AVREF = 5.0V VSS = AVSS = 0V -50 4910 10 4970 Symbol Pin Condition Min. Typ. Max. 8 3 70 5030 5 70 3345 Unit Bits LSB mV mV LSB mV mV s s V V V mA mA A
tCONV tSAMP
VREF VIAN IREF
AVREF current
Fig.6. Definition of A/D converter terms 1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEH). CKS
VZT Analog input VFT
FFH FEH
Digital conversion value
Linearity error 01H 00H
PCK1, PCK0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
0(/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1( selection) fADC = fC fADC = fC/2 fADC = fC/8
- 23 -
CXP84632/84640/84648
(4) Interruption, reset input (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin INT0 INT1 INT2 INT3 INT4 NMI RST Condition Min. Max. Unit
External interruption HIgh, Low level width
tIH tIL
1
s
Reset input Low level width
tRSL
32/fc
s
Fig. 7. Interruption input timing
tIH tIL
INT0 INT1 INT2 INT3 INT4 NMI (NMI is specified only for the falling edge)
0.8VDD 0.2VDD tIL tIH
Fig. 8. RST input timing
tRSL
RST 0.2VDD
- 24 -
CXP84632/84640/84648
(5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data bold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion Symbol fSLC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.
Fig. 9. I2C bus transfer timing
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 10. Recommended circuit example for I2C device
I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C device RS RP RP
* Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * Serial resistance (Rs = 300 or less) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flash-over.
- 25 -
CXP84632/84640/84648
Appendix Fig. 11. SPC700 Series recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5 5
0
(i)
0 0 0 470k (ii) (i)
HC-49/U (-S) KINSEKI LTD.
10.00 12.00 16.00
P3
32.768kHz
Mask option table Item Reset pin pull-up resistor Content Non-existent Existent
- 26 -
CXP84632/84640/84648
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical)
IDD vs. VDD
(fc = 12MHz, Ta = 25C, Typical)
50.0 1/2 frequency mode 1/4 frequency mode 10.0 5.0
50.0 1/2 frequency mode 10.0 1/16 frequency mode 5.0 1/16 frequency mode SLEEP mode 1/4 frequency mode
IDD-Supply current [mA]
IDD-Supply current [mA]
1.0 0.5
1.0 0.5
SLEEP mode
32kHz mode (instruction)
0.1 (100A) 0.05 (50A)
32kHz SLEEP mode
0.1 (100A) 0.05 (50A)
0.01 (10A)
0.01 (10A)
3
4
5
6
3
4
5
6
VDD-Supply voltage [V]
VDD-Supply voltage [V]
IDD vs. fc
(VDD = 5.0V, Ta = 25C, Typical)
IDD vs. fc
(VDD = 3.3V, Ta = 25C, Typical)
30 1/2 frequency mode
30
IDD-Supply current [mA]
20
IDD-Supply current [mA]
20
1/2 frequency mode 10
1/4 frequency mode 10 1/16 frequency mode SLEEP mode 1 5 10 15 16
1/4 frequency mode 1/16 frequency mode SLEEP mode 1 5 10 15 16 fc-System clock [MHz]
0
0
fc-System clock [MHz]
- 27 -
CXP84632/84640/84648
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
- 28 -
0.8 0.2
1
24
16.3

▲Up To Search▲

Price & Availability of CXP84632

	To Download CXP84632 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .